The present invention relates most generally to semiconductor devices and methods for forming the same. More particularly, the present invention relates to a method for forming shallow trench isolation structures.
In today""s advancing semiconductor manufacturing processing technology, the multitude of components which combine to form an integrated circuit device are being formed in increasingly closer proximity. In order to avoid adjacent devices from shorting to one another, and in order to avoid leakage between devices formed in close proximity to one another, shallow trench isolation (STI) structures have become a commonly used feature in the semiconductor manufacturing industry.
The process for forming an STI structure typically involves forming a trench-like opening in a silicon substrate, then filling the trench opening with an insulating material. The insulating materials may be formed by deposition techniques such as low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) deposition, or any other suitable method for depositing an insulating material within a trench opening. After the opening is filled with a deposited insulating material, a planarizing process such as chemical mechanical polishing (CMP) is used to planarize the surface by removing any portions of the insulating material which may be formed above the upper plane beneath which the trench opening extends.
Nitride (silicon nitridexe2x80x94Si3N4) or other oxidation resistant, and suitably hard films, are typically used as hard masks for trench-formation silicon etches and also as polishing stop layers for CMP operations. In this manner, the to nitride or other, hard, oxidation-resistant film forms the upper surface beneath which the trench opening extends. Hard films are favored because of their resistance as well as selectivity during the polishing operations used to planarize the STI structures. Such films have relatively low removal rates and may be referred to as polishing stop layers.
During the formation of STI structures, problems arise when the polishing operations used to polish the insulating material and planarize the STI structure, cause xe2x80x9cdishingxe2x80x9d on the top of the STI structure. Dishing describes the phenomena wherein the top surface of the insulating material within the trench, becomes recessed below the upper surface of the polishing stop layer such as silicon nitride. Typically, the central portion of the top surface of the STI structure is recessed below the peripheral portion of the top surface of the STI structure. The peripheral edges of the STI structure generally extend up the side of the trench opening to intersect the upper surface of the polishing stop layer at the edges of the trench opening. Sharp, upward projections of the insulating material may therefore result at these peripheral edges. The central portion of the top surface of the STI structure may be recessed by as many as 500 angstroms with respect to the edges of the STI structure. After the nitride polishing-stop layer is subsequently removed and the entire top portion of the STI structure uniformly recessed, the 500 angstrom height difference on the top of the STI structure, remains.
After the STI structure is completed, the sharp, upward projections may remain at the edges of the STI structure which may additionally extend above the upper surface of the semiconductor substrate. These projections may extend above the bulk of the STI structure by as much as 500 angstroms, and may extend above the surrounding semiconductor substrate by an even greater distance. Polysilicon films are commonly used to form transistor gates and to serve other interconnection functions in semiconductor integrated circuits. At the location where the polysilicon film extends over the sharp upward projections created at the peripheries of STI structures due to dishing, a localized electric field is created. Such a localized electric field is highly undesirable as it may produce various electrical parametric problems throughout the device. For example, such an electric field formed in a transistor gate may lower the threshold voltage, Vt, for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. These sharp upward projections in the STI structure created by dishing can cause other electrical problems which may result in device failure, or which may require additional implants to compensate for changed parametric characteristics, or both.
It can therefore be seen that there is a need for a process for forming shallow trench isolation structures having planar upper surfaces and which do not have sharp projections which extend upward and can create localized electric fields.
To achieve these and other objects, and in view of its purposes, the present invention addresses the shortcomings of the processes for forming shallow trench isolation structures known to the prior art and provides an improved process for forming superior shallow trench isolation structures. The present invention describes materials, processes, and structures used to produce low leakage STI structures having substantially planar upper surfaces. The present invention provides a method for filling the voids created due to dishing. The voids are filled by a silicon-containing film which, in its as-deposited or oxidized form, provides a material having polishing characteristics which are similar to those of the film used as the polishing-stop layer. After the voids are filled, a subsequent polishing step is used to form a substantially planarized upper surface of the shallow trench isolation structure. Such a planarized structure results because the polishing rate of the silicon film or oxidized silicon film is much more similar to that of the polishing-stop layer than was the polishing rate of the dielectric material originally formed within the trench opening. The production of shallow trench isolation structures having planar upper surfaces eliminates the subsequent formation of localized electric fields and therefore produces devices which are less prone to leakage and other parametric failures.
It is to be understood that both the foregoing general description and the following detailed descriptions are exemplary, but not restrictive of the invention.